bit parallel
英 [bɪt ˈpærəlel]
美 [bɪt ˈpærəlel]
网络 位并行
双语例句
- When the Security Bit is activated all parallel PROGRAMMING commands except for Chip-Erase are ignored ( thus the DEVICE cannot be read).
当保密位被激活后，除芯片擦除外的所有并行编程命令都被忽略（这样就不能对器件执行读操作）。 - Design of a 8 Bit Parallel Interpolation Analog to Digital Converter
一种八位并行插值型模数转换器的设计 - Monolithic Integrated 16 × 16 bit Multiplier Operating in Parallel and Pipeline
单片集成并行流水线操作16×16位数字乘法器 - For example, a device that converts between bit serial and bit parallel and resolves differences in transmission speeds.
例如，一台在串行位和并行位之间作转换且解决传输速度差别的设备。 - Bit Allocation Strategy for Parallel HDTV Video Encoder
HDTV视频编码器的动态图像组结构和码率分配策略 - Design of Bit Parallel RS Encoder Based on Weak Dual Basis
弱对偶基下比特并行RS编码器的设计 - Design of 16 Bit Parallel Data Communication Interface
双机16位并行通讯电路设计 - Design and Applications of 16 bit Parallel Interface Model for IEEE-696/ S-100
IEEE696/S100十六位并行接口模板设计与应用 - The compression ratio of algorithm is more than 1.9. The compression algorithm based on bit plane transform can be realized by parallel computing model.
压缩比达到了1.9以上，与其它超光谱图像压缩算法相当。位平面变换算法具有很好的并行性。 - This paper introduces the vector mode of CORDIC algorithm and draw a comparison between bit serial iterative CORDIC and bit parallel iterative CORDIC. We propose method of solving overflow of bit serial iterative CORDIC and design the architecture of bit serial iterative CORDIC.
介绍了CORDIC算法理论的矢量模式，在分析比较得出位串行CORDIC结构优于位并行CORDIC结构之处的基础上，提出了解决位串行迭代结构溢出的方法，并设计了结构图。 - The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
说明了对偶基比特并行乘法器在硬件规模上的优越性。 - In this paper, an 8 bit parallel ATM scrambler ( descrambler) is designed by using the theory of the matrix algorithm, it reduces the speed of the circuits greatly.
运用矩阵算法设计了8bit并行ATM扰码（解扰）器，大大降低了电路的处理速度。 - The principle of 16 × 16 bit multiplier operating in parallel and pipeline and controlled by two nonoverlapping pulses is described.
本文介绍采用平行/流水线操作原理的16×16位数字乘法器的工作原理和单片集成结果。 - In this paper we briefly introduce some basic concepts of quantum computing which include quantum entanglement, quantum bit, quantum register, quantum parallel computing and quantum error correction.
本文简要地介绍量子计算的一些基本概念：量子纠缠、量子位、量子寄存器、量子并行计算和量子纠错。 - Based on these, an algorithm to optimize MDS codes is introduced by analyzing the complexity of bit parallel multipliers.
在此基础上，借助于对比特级并行乘法器的复杂度的分析，给出了一个优化最大距离可分码的算法。 - Study and Design of Floating-point 32 Bit Parallel Multiplier
浮点32位并行乘法器设计与研究 - The replacement type ADC, formed by m grades × n bits ADC, it needs just one set of n bit full parallel type ADC and converts the analog voltage signal into the digital signal.
置换式ADC，以组成m级×n位ADC为例，仅需一套n位的全并行式ADC，直接将模拟电压信号转换成数字信号； - The FPDP bus is a 32 bit parallel synchronous bus intended to provide high speed data transfer among multiple VME bus boards. The FPDP bus design does not allow for the transmission of address information.
FPDP总线为32位的并行同步总线，提供多块VME总线板之间的高速数据传输，总线设计不允许地址信息传递。 - Secondly, the short-wave MODEM hardware platform. based-on DSP is developed, and on the basis of which, the algorithms such as. bit synchronization algorithm, multi-channel parallel modulation and demodulation algorithm, and CRC-16 table lookup algorithm are implemented.
设计了基于DSP的短波调制解调器硬件系统，并在此硬件系统上实现了位同步提取算法、多路并行调制解训算法以及CRC-16的查表快速算法等核心算法。 - Design of Bit Parallel Reed Solomon Encoder
比特并行Reed-Solomon编码器的设计 - This paper introduces dual basis bit parallel multiplier-a kind of multiplier suitable for Reed-Solomon encoder and decoder in HDTV, being emphasized in its algorithm and design plan.
重点介绍了一种适合HDTV的RS码编译码器乘法器：对偶基比特并行乘法器的算法和实现方案。 - An efficient design method for a 24 × 24 bit+ 48 bit parallel saturating multiply-accumulate ( MAC) unit is described.
阐述了一种24×24bit+48bit带饱和处理的乘加单元的优化设计。 - Design of an 8-Bit Parallel Multiplier Using FPGA
采用FPGA实现的8位高速并行乘法器 - 20 Bit Σ△ ADC Connecting With Parallel Port Of PC
利用PC的并行端口实现与20比特∑△型ADC的连接 - A Extension Bit Method for Parallel Frame Synchronous Scrambler
并行帧同步扰码器的扩充比特设计法 - By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used RS decoder is constructed.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。 - The paper elaborated on the register configuration of the digital control circuit module, and send data to the control logic state machine, the NRZI module, bit stuffing module, parallel to serial module implementation of principles and methods.
论文详细阐述了数字控制电路中的寄存器配置模块、数据发送控制逻辑状态机、反转不归零编码模块、比特填充器模块、并行转串行模块的实现原理和方法。 - The compression algorithm based on bit plane transform can be realized by parallel computing model.
位平面变换算法具有很好的并行性。